1. Field of the Invention
The present invention relates to quadrature modulation and demodulation in high-speed wireless communications, and particularly to detection of a phase shift between an I data clock and a Q data clock in Digital-Analog Converters (DACs) or Analog-Digital Converters (ADCs) used in a modulator or demodulator and correction of the phase shift.
2. Description of the Related Art
Modulation is an operational scheme where during the transmission of information, the information is converted into appropriate electric signals according to the information type and the transmission medium. Demodulation is the restoration of an original signal wave from the modulated signal upon receipt of the transmitted modulated signal. In information transmission in wireless communications, the transmitter side modulates data to be transmitted and outputs the modulated data, and the receiver side receives and demodulates the data transmitted as radio waves.
A quadrature modulator converts data to be transmitted into I and Q signals by using a conversion table, and inputs the I and Q signals into an I-DAC (DAC: digital-to-analog converter) and a Q-DAC, respectively. An analog modulated signal I outputted from the I-DAC is multiplied by a carrier wave, and an analog modulated signal Q outputted from the Q-DAC is multiplied by a carrier wave which is out of phase by 90° with the carrier wave for the analog modulated signal I. The I and Q signals are then combined and outputted as a modulated signal. The technical definition of quadrature is to generate signals having no correlation with each other by multiplying two signals that are obtained by dividing an original signal by a sine wave and a cosine wave, respectively, and to add these two signals together and send the signal thus combined.
The analog modulated signal I outputted from the I-DAC and the analog modulated signal Q outputted from the Q-DAC have to be in exact synchronization with each other. To achieve the synchronization, an I data clock generated by the I-DAC and a Q data clock generated by the Q-DAC must be in phase with each other based on a sampling clock inputted to the I-DAC and the Q-DAC.
In Non-patent Literature 1 (Shergill, “A 6 Gs/s, 8-bit Data Acquisition Channel Using National Ultra-High-Speed ADCs,” National Semiconductor, Application Note, 2008, pp. 1-27), the I-DAC and the Q-DAC are reset simultaneously so that the data clock from the I-DAC and the data clock from the Q-DAC can be in phase. However, this is not easy because they have to be reset in synchronization with a high-frequency sampling clock. Thus, a determination has to be made as to whether the reset has successfully brought the data clocks into the same phase.
In Non-patent Literature 2 (Maxim, “12-Bit 4.0 Gsps High-Dynamic Performance Wideband DAC,” Data Sheet, 2008, pp. 1-23), since the DACs do not have a reset input function, the data transmitter side has to change the order of data transmission upon detecting the phase shift between the data clocks.
In Non-patent Literature 3 (Maxim, “Synchronizing Multiple High-Speed Multiplexed DACs for Transmit Applications,” Application Note, 2006, pp. 1-6), clock swallowing is employed, which momentarily stops the sampling clock inputted to the I-DAC when the value obtained by performing XORing (exclusive ORing) on the data clock from the I-DAC and the data clock from the Q-DAC is 1. However, since the digital logic is inserted directly into the sampling clock circuit, the sampling clocks reaching the I-DAC and the Q-DAC tend to have skew. Further, the logic (active device) increases jitter.
Non-patent Literature 3 introduces a method of phase alignment by giving a data clock feedback to a PLL (phase-locked loop) that generates the sampling clock. However, a voltage controlled oscillator (VCO) used in the PLL degrades frequency stability. Moreover, since the I-DAC and Q-DAC use independent PLLs, the frequency shift and skew can be large. Non-patent Literature 3 also introduces a method of using a phase shifting function of a digital clock manager (DCM) of Xilinx FPGA to compare the data clocks while gradually delaying one of the data clocks. However, the maximum phase-controllable frequency of the DCM is 400 MHz even with the highest speed grade of the latest Virtex-5, and therefore a usable frequency is limited.
Non-patent Literature 4 (Texas Instruments, “Digital Phase-Locked Loop Design Using SN54/74LS297,” Application Note, SDLA005B, March 1997, pp. 1-15), introduces a phase comparator used in a digital phase-locked loop (DPLL). The phase comparator performs M-time oversampling of the XOR output. M is one of the conditions for the DPLL to be locked, and has to be larger than 1 and as large as possible (sampling frequency must be larger than the clock).